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PD -97148
IRLS3036-7PPBF
HEXFET(R) Power MOSFET
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Applications l DC Motor Drive l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching G l Hard Switched and High Frequency Circuits Benefits l Optimized for Logic Level Drive l Very Low RDS(ON) at 4.5V VGS l Superior R*Q at 4.5V VGS l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
D
S
VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited)
60V 1.5m: 1.9m: 300Ac 240A
D
S G S S
S
S
D2Pak 7 Pin
G
D
S
Gate
Drain
Max.
300c 210 240 1000 380 2.5 16 8.1 -55 to + 175 300 300 See Fig. 14, 15, 22a, 22b
Source
Units
A
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Package Limited) Pulsed Drain Current d Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery f Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case)
W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy e Avalanche Current d Repetitive Avalanche Energy d mJ A mJ
Thermal Resistance
Symbol
RJC RJA
Parameter
Junction-to-Case kl Junction-to-Ambient (PCB Mount, steady state) j
Typ.
--- ---
Max.
0.40 40
Units
C/W
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1
12/8/08
IRLS3036-7PPBF
Static @ TJ = 25C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
60 --- --- --- 1.0 --- --- --- ---
---
Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage V(BR)DSS/TJ Breakdown Voltage Temp. Coefficient RDS(on) IDSS IGSS RG(int) Static Drain-to-Source On-Resistance
VGS(th) Gate www..com Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
--- --- V VGS = 0V, ID = 250A 0.059 --- V/C Reference to 25C, ID = 5mAd 1.5 1.9 VGS = 10V, ID = 180A g m VGS = 4.5V, ID = 150A g 1.7 2.2 --- 2.5 V VDS = VGS, ID = 250A --- 20 VDS = 60V, VGS = 0V A --- 250 VDS = 60V, VGS = 0V, TJ = 125C --- 100 VGS = 16V nA --- -100 VGS = -16V 1.9 ---
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Effective Output Capacitance (Energy Related)i Effective Output Capacitance (Time Related) h
Min. Typ. Max. Units
390 --- --- --- 110 160 --- 33 --- --- 53 --- --- 57 --- --- 81 --- --- 540 --- --- 89 --- --- 170 --- --- 11270 --- --- 1025 --- --- 520 --- --- 1460 --- --- 1630 --- S
Conditions
VDS = 10V, ID = 180A ID = 180A VDS = 30V nC VGS = 4.5V g ID = 180A, VDS =0V, VGS = 4.5V VDD = 39V ID = 180A ns RG = 2.1 VGS = 4.5V g VGS = 0V VDS = 50V pF = 1.0MHz VGS = 0V, VDS = 0V to 48V i VGS = 0V, VDS = 0V to 48V h
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Notes:
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) e Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 300 A 1000
Conditions
MOSFET symbol showing the integral reverse
G S D
--- --- 1.3 V --- 57 --- ns --- 60 --- --- 140 --- nC TJ = 125C --- 160 --- --- 4.6 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25C, IS = 180A, VGS = 0V g VR = 51V, TJ = 25C IF = 180A TJ = 125C di/dt = 100A/s g TJ = 25C
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.018mH RG = 25, IAS = 180A, VGS =10V. Part not recommended for use above this value . ISD 180A, di/dt 1070A/s, VDD V(BR)DSS, TJ 175C.
Pulse width 400s; duty cycle 2%. Coss eff. (TR) is a fixed capacitance that gives the same charging time as
Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For
Coss while VDS is rising from 0 to 80% VDSS. recommended footprint and soldering techniquea refer to applocation note # AN- 994 echniques refer to application note #AN-994. R is measured at TJ approximately 90C. RJC value shown is at time zero.
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IRLS3036-7PPBF
1000
TOP VGS 15V 10V 4.5V 4.0V 3.5V 3.3V 3.0V 2.7V
1000
TOP VGS 15V 10V 4.5V 4.0V 3.5V 3.3V 3.0V 2.7V
ID, Drain-to-Source Current (A)
100
BOTTOM
ID, Drain-to-Source Current (A)
BOTTOM
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10
100
1
2.7V 60s PULSE WIDTH Tj = 25C
2.7V 60s PULSE WIDTH Tj = 175C
10 0.1 1 10 100
0.1 0.1 1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
2.5
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
ID = 180A
2.0
ID, Drain-to-Source Current()
VGS = 10V
TJ = 175C
100
(Normalized)
1.5
TJ = 25C
10
1.0
VDS = 25V
1 2.0 3.0
60s PULSE WIDTH
4.0 5.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
20000 VGS = 0V, f = 100 kHz Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
5
VGS, Gate-to-Source Voltage (V)
ID= 180A 4
VDS = 48V VDS = 30V
15000
C, Capacitance (pF)
Ciss
10000
3
2
5000
Coss Crss
1
0 1 10 100
0 0 20 40 60 80 100 120 140 QG Total Gate Charge (nC)
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRLS3036-7PPBF
1000
10000
ID, Drain-to-Source Current (A)
TJ = 175C
OPERATION IN THIS AREA LIMITED BY R DS (on) 100sec
ISD , Reverse Drain Current (A)
100
1000
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10
TJ = 25C
100 1msec 10
LIMITED BY PACKAGE
10msec 1 Tc = 25C Tj = 175C Single Pulse 0.1 1
1
VGS = 0V
0.1 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
DC
0.1 10 100
VSD , Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
300 LIMITED BY PACKAGE 250
ID , Drain Current (A)
V(BR)DSS , Drain-to-Source Breakdown Voltage
80
Fig 8. Maximum Safe Operating Area
ID = 5mA
200 150 100 50 0 25 50 75 100 125 150 175 TC , Case Temperature (C)
70
60
50 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
Fig 9. Maximum Drain Current vs. Case Temperature
4.0
TJ , Junction Temperature (C)
Fig 10. Drain-to-Source Breakdown Voltage
1200
EAS, Single Pulse Avalanche Energy (mJ)
1000
3.0
ID 22A 37A BOTTOM 180A
TOP
800
Energy (J)
2.0
600
400
1.0
200
0.0 0 10 20 30 40 50 60 70
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRLS3036-7PPBF
1
D = 0.50
Thermal Response ( Z thJC )
0.1
0.20 0.10 0.05 0.02 0.01
J R1 R1 J 1 2 R2 R2 R3 R3 C 1 2 3 3
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0.01
Ri (C/W)
(sec)
Ci= i/Ri Ci= i/Ri
0.103731 0.000184 0.196542 0.001587 0.098271 0.006721
0.001
SINGLE PULSE ( THERMAL RESPONSE )
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01 0.1
0.0001 1E-006 1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Avalanche Current (A)
100
0.01 0.05 0.10
10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
300
EAR , Avalanche Energy (mJ)
250
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 180A
200
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150
Starting TJ , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRLS3036-7PPBF
3.0
24
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
2.5
ID = 1.0mA ID = 250A
18
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2.0
IRRM - (A)
12
1.5
6
IF = 120A VR = 51V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
0
TJ , Temperature ( C )
dif / dt - (A / s)
Fig 16. Threshold Voltage Vs. Temperature
24
Fig. 17 - Typical Recovery Current vs. dif/dt
1000
800 18
QRR - (nC)
IRRM - (A)
600
12
400 IF = 120A VR = 51V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900
6
IF = 180A VR = 51V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900
200
0
0
dif / dt - (A / s)
dif / dt - (A / s)
Fig. 18 - Typical Recovery Current vs. dif/dt
1000 IF = 180A VR = 51V TJ = 125C TJ = 25C
Fig. 19 - Typical Stored Charge vs. dif/dt
800
QRR - (nC)
600
400
200
0 100 200 300 400 500 600 700 800 900
dif / dt - (A / s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRLS3036-7PPBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
-
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+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRLS3036-7PPBF
D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
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Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
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IRLS3036-7PPBF
D2Pak - 7 Pin Part Marking Information
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25
D2Pak - 7 Pin Tape and Reel
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 12/08
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